32x32 pixel ROIC array for counting applications

The readout circuit  (ROIC) array is designed  to be assembled in flip-chip with aPeak's GPD arrays or RCGPD arrays. Pixel pitch is 130um x 130um. The smart pixel technology includes at pixel level 1 active quenching circuit, 32 clock tick afterpulsing control, 8-bit counters capable of up/down counting (for background and noise on-chip correction), event memory and shift registers for data out. An on-chip, data read twin-driver allows either full array read (32 column parallel read) or 2X readout rate by enabling serial-parallel read of the two, on-chip16x32 pixel sub-arrays (64 column parallel read). Maximum design clock rate is 160MHZ. Typical power at 20MHz and Vcc=2.5V is 3W. Data acquisition time is controlled by user. Whole array readout time is 10 x Nrows x CLOCK (e.g. for Nrows =32 rows and CLOCK=6ns or 50ns readout time is 1.92us or 16us respectively).

Minimum order applies for customized ROIC array and matching GPD array specifications.