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16x32 pixel ROIC array with Time to Digital Converters (TDC) at pixel level

The readout circuit  (ROIC) array is designed for LADAR/ranging applications.The ROIC is designed  to be assembled in flip-chip with aPeak's GPD arrays or RCGPD arrays. Pixel pitch is 200um x 200um. The smart pixel technology includes at pixel level one active quenching circuit (AQC) with fixed pulse width (50ns), 7-bit timing vernier (fine range) and 11-bit LFSR (rough range). In asynchronous applications like LADAR, flash-LADAR timing violations in the vernier decrease the laser utilization efficiency and increase the burden on post-acquisition 3D image processing. Redundancy in the timing vernier allows decreasing the fraction of timing violations and improving on the 3D image. An on-chip, data read driver allows  full array read (32 column parallel read). Maximum design clock rate is160MHZ. Data acquisition time is controlled by user based on target range. Whole array readout time is 20 x Nrows x CLOCK (e.g. for Nrows =32 rows and CLOCK=6ns or 50ns. the readout time is 3.84us or 32us respectively).

Minimum order applies for customized ROIC array and GPD array specifications. For cost-eftective larger array assembly we recommend stitching (see below).

 

         

(a) 16x32 pixel ROIC TDC array die for bump bonding assembly  with GPD arrays; (b) The layout of the 16x32 pixel ROIC is designed to allow assembling  four 16x32 channel ROIC TDC dies with minimal gap.

 

aPeak Inc., Newton, MA 02466  Telephone: 617-964-1709

email:  info@apeakinc.com

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